The present invention relates to a decoder for a D/A converter.
In a D/A converter used for digitally processing television signals, (2.sup.n -1) pairs of current sources and switches are provided in a parallel fashion for the digital input of n bits. The number of switches turned on is given by the digital expression of the digital input. A decoder is used for generating the bit data necessary for controlling the (2.sup.n -1) switches according to the n bit digital input. One of such decoders has been proposed in "The Institute of Electronics and Communication Engineers", vol. 82, No. 13, SSD 82-1. The proposed decoder is as shown in FIG. 1. An arrangement is provided which is composed of input buffers 1.sub.1 to 1.sub.4, first and second ladder circuits, and eight differential amplifiers 4.sub.1 to 4.sub.8. The 4-bit digital input B1 to B4 is converted into 16 analog signals by this arrangement. These converted signals are combined into a plurality of pairs. These paired signals are compared with every other pair and are held to have the logic " 1" or "0" according to the result of the comparison.
In the above decoder, eight amplifiers 4.sub.1 to 4.sub.8 are used. Accordingly, the number of elements required is large enough to complicate the circuit construction, to increase the cost of manufacture, and to decrease the operation speed. When the digital input changes from (0000) to (1111), an analog signal changes from a level V.sub.B to a maximum level V.sub.D, and another analog signal changes from a level V.sub.C to a minimum level V.sub.A. Of these levels, the difference between the maximum and minimum levels is large, but the difference between the levels V.sub.B and V.sub.C is very small. Accordingly, when the power source voltage is low, it is very difficult to produce a level between them sufficient enough to compare the signals V.sub.21 and V.sub.22. Therefore, the efficiency when using the low power source voltage is poor.